AN_BITFIELD
		uint64_t reserved_37_63:27;
		uint64_t fcnt:5;
		uint64_t avail:32;
#else
		uint64_t avail:32;
		uint64_t fcnt:5;
		uint64_t reserved_37_63:27;
#endif
	} s;
};

union cvmx_npi_pci_burst_size {
	uint64_t u64;
	struct cvmx_npi_pci_burst_size_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t wr_brst:7;
		uint64_t rd_brst:7;
#else
		uint64_t rd_brst:7;
		uint64_t wr_brst:7;
		uint64_t reserved_14_63:50;
#endif
	} s;
};

union cvmx_npi_pci_int_arb_cfg {
	uint64_t u64;
	struct cvmx_npi_pci_int_arb_cfg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t hostmode:1;
		uint64_t pci_ovr:4;
		uint64_t reserved_5_7:3;
		uint64_t en:1;
		uint64_t park_mod:1;
		uint64_t park_dev:3;
#else
		uint64_t park_dev:3;
		uint64_t park_mod:1;
		uint64_t en:1;
		uint64_t reserved_5_7:3;
		uint64_t pci_ovr:4;
		uint64_t hostmode:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
	struct cvmx_npi_pci_int_arb_cfg_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_5_63:59;
		uint64_t en:1;
		uint64_t park_mod:1;
		uint64_t park_dev:3;
#else
		uint64_t park_dev:3;
		uint64_t park_mod:1;
		uint64_t en:1;
		uint64_t reserved_5_63:59;
#endif
	} cn30xx;
};

union cvmx_npi_pci_read_cmd {
	uint64_t u64;
	struct cvmx_npi_pci_read_cmd_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_11_63:53;
		uint64_t cmd_size:11;
#else
		uint64_t cmd_size:11;
		uint64_t reserved_11_63:53;
#endif
	} s;
};

union cvmx_npi_port32_instr_hdr {
	uint64_t u64;
	struct cvmx_npi_port32_instr_hdr_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_44_63:20;
		uint64_t pbp:1;
		uint64_t rsv_f:5;
		uint64_t rparmode:2;
		uint64_t rsv_e:1;
		uint64_t rskp_len:7;
		uint64_t rsv_d:6;
		uint64_t use_ihdr:1;
		uint64_t rsv_c:5;
		uint64_t par_mode:2;
		uint64_t rsv_b:1;
		uint64_t skp_len:7;
		uint64_t rsv_a:6;
#else
		uint64_t rsv_a:6;
		uint64_t skp_len:7;
		uint64_t rsv_b:1;
		uint64_t par_mode:2;
		uint64_t rsv_c:5;
		uint64_t use_ihdr:1;
		uint64_t rsv_d:6;
		uint64_t rskp_len:7;
		uint64_t rsv_e:1;
		uint64_t rparmode:2;
		uint64_t rsv_f:5;
		uint64_t pbp:1;
		uint64_t reserved_44_63:20;
#endif
	} s;
};

union cvmx_npi_port33_instr_hdr {
	uint64_t u64;
	struct cvmx_npi_port33_instr_hdr_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_44_63:20;
		uint64_t pbp:1;
		uint64_t rsv_f:5;
		uint64_t rparmode:2;
		uint64_t rsv_e:1;
		uint64_t rskp_len:7;
		uint64_t rsv_d:6;
		uint64_t use_ihdr:1;
		uint64_t rsv_c:5;
		uint64_t par_mode:2;
		uint64_t rsv_b:1;
		uint64_t skp_len:7;
		uint64_t rsv_a:6;
#else
		uint64_t rsv_a:6;
		uint64_t skp_len:7;
		uint64_t rsv_b:1;
		uint64_t par_mode:2;
		uint64_t rsv_c:5;
		uint64_t use_ihdr:1;
		uint64_t rsv_d:6;
		uint64_t rskp_len:7;
		uint64_t rsv_e:1;
		uint64_t rparmode:2;
		uint64_t rsv_f:5;
		uint64_t pbp:1;
		uint64_t reserved_44_63:20;
#endif
	} s;
};

union cvmx_npi_port34_instr_hdr {
	uint64_t u64;
	struct cvmx_npi_port34_instr_hdr_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_44_63:20;
		uint64_t pbp:1;
		uint64_t rsv_f:5;
		uint64_t rparmode:2;
		uint64_t rsv_e:1;
		uint64_t rskp_len:7;
		uint64_t rsv_d:6;
		uint64_t use_ihdr:1;
		uint64_t rsv_c:5;
		uint64_t par_mode:2;
		uint64_t rsv_b:1;
		uint64_t skp_len:7;
		uint64_t rsv_a:6;
#else
		uint64_t rsv_a:6;
		uint64_t skp_len:7;
		uint64_t rsv_b:1;
		uint64_t par_mode:2;
		uint64_t rsv_c:5;
		uint64_t use_ihdr:1;
		uint64_t rsv_d:6;
		uint64_t rskp_len:7;
		uint64_t rsv_e:1;
		uint64_t rparmode:2;
		uint64_t rsv_f:5;
		uint64_t pbp:1;
		uint64_t reserved_44_63:20;
#endif
	} s;
};

union cvmx_npi_port35_instr_hdr {
	uint64_t u64;
	struct cvmx_npi_port35_instr_hdr_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_44_63:20;
		uint64_t pbp:1;
		uint64_t rsv_f:5;
		uint64_t rparmode:2;
		uint64_t rsv_e:1;
		uint64_t rskp_len:7;
		uint64_t rsv_d:6;
		uint64_t use_ihdr:1;
		uint64_t rsv_c:5;
		uint64_t par_mode:2;
		uint64_t rsv_b:1;
		uint64_t skp_len:7;
		uint64_t rsv_a:6;
#else
		uint64_t rsv_a:6;
		uint64_t skp_len:7;
		uint64_t rsv_b:1;
		uint64_t par_mode:2;
		uint64_t rsv_c:5;
		uint64_t use_ihdr:1;
		uint64_t rsv_d:6;
		uint64_t rskp_len:7;
		uint64_t rsv_e:1;
		uint64_t rparmode:2;
		uint64_t rsv_f:5;
		uint64_t pbp:1;
		uint64_t reserved_44_63:20;
#endif
	} s;
};

union cvmx_npi_port_bp_control {
	uint64_t u64;
	struct cvmx_npi_port_bp_control_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t bp_on:4;
		uint64_t enb:4;
#else
		uint64_t enb:4;
		uint64_t bp_on:4;
		uint64_t reserved_8_63:56;
#endif
	} s;
};

union cvmx_npi_rsl_int_blocks {
	uint64_t u64;
	struct cvmx_npi_rsl_int_blocks_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t rint_31:1;
		uint64_t iob:1;
		uint64_t reserved_28_29:2;
		uint64_t rint_27:1;
		uint64_t rint_26:1;
		uint64_t rint_25:1;
		uint64_t rint_24:1;
		uint64_t asx1:1;
		uint64_t asx0:1;
		uint64_t rint_21:1;
		uint64_t pip:1;
		uint64_t spx1:1;
		uint64_t spx0:1;
		uint64_t lmc:1;
		uint64_t l2c:1;
		uint64_t rint_15:1;
		uint64_t reserved_13_14:2;
		uint64_t pow:1;
		uint64_t tim:1;
		uint64_t pko:1;
		uint64_t ipd:1;
		uint64_t rint_8:1;
		uint64_t zip:1;
		uint64_t dfa:1;
		uint64_t fpa:1;
		uint64_t key:1;
		uint64_t npi:1;
		uint64_t gmx1:1;
		uint64_t gmx0:1;
		uint64_t mio:1;
#else
		uint64_t mio:1;
		uint64_t gmx0:1;
		uint64_t gmx1:1;
		uint64_t npi:1;
		uint64_t key:1;
		uint64_t fpa:1;
		uint64_t dfa:1;
		uint64_t zip:1;
		uint64_t rint_8:1;
		uint64_t ipd:1;
		uint64_t pko:1;
		uint64_t tim:1;
		uint64_t pow:1;
		uint64_t reserved_13_14:2;
		uint64_t rint_15:1;
		uint64_t l2c:1;
		uint64_t lmc:1;
		uint64_t spx0:1;
		uint64_t spx1:1;
		uint64_t pip:1;
		uint64_t rint_21:1;
		uint64_t asx0:1;
		uint64_t asx1:1;
		uint64_t rint_24:1;
		uint64_t rint_25:1;
		uint64_t rint_26:1;
		uint64_t rint_27:1;
		uint64_t reserved_28_29:2;
		uint64_t iob:1;
		uint64_t rint_31:1;
		uint64_t reserved_32_63:32;
#endif
	} s;
	struct cvmx_npi_rsl_int_blocks_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t rint_31:1;
		uint64_t iob:1;
		uint64_t rint_29:1;
		uint64_t rint_28:1;
		uint64_t rint_27:1;
		uint64_t rint_26:1;
		uint64_t rint_25:1;
		uint64_t rint_24:1;
		uint64_t asx1:1;
		uint64_t asx0:1;
		uint64_t rint_21:1;
		uint64_t pip:1;
		uint64_t spx1:1;
		uint64_t spx0:1;
		uint64_t lmc:1;
		uint64_t l2c:1;
		uint64_t rint_15:1;
		uint64_t rint_14:1;
		uint64_t usb:1;
		uint64_t pow:1;
		uint64_t tim:1;
		uint64_t pko:1;
		uint64_t ipd:1;
		uint64_t rint_8:1;
		uint64_t zip:1;
		uint64_t dfa:1;
		uint64_t fpa:1;
		uint64_t key:1;
		uint64_t npi:1;
		uint64_t gmx1:1;
		uint64_t gmx0:1;
		uint64_t mio:1;
#else
		uint64_t mio:1;
		uint64_t gmx0:1;
		uint64_t gmx1:1;
		uint64_t npi:1;
		uint64_t key:1;
		uint64_t fpa:1;
		uint64_t dfa:1;
		uint64_t zip:1;
		uint64_t rint_8:1;
		uint64_t ipd:1;
		uint64_t pko:1;
		uint64_t tim:1;
		uint64_t pow:1;
		uint64_t usb:1;
		uint64_t rint_14:1;
		uint64_t rint_15:1;
		uint64_t l2c:1;
		uint64_t lmc:1;
		uint64_t spx0:1;
		uint64_t spx1:1;
		uint64_t pip:1;
		uint64_t rint_21:1;
		uint64_t asx0:1;
		uint64_t asx1:1;
		uint64_t rint_24:1;
		uint64_t rint_25:1;
		uint64_t rint_26:1;
		uint64_t rint_27:1;
		uint64_t rint_28:1;
		uint64_t rint_29:1;
		uint64_t iob:1;
		uint64_t rint_31:1;
		uint64_t reserved_32_63:32;
#endif
	} cn30xx;
	struct cvmx_npi_rsl_int_blocks_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t rint_31:1;
		uint64_t iob:1;
		uint64_t rint_29:1;
		uint64_t rint_28:1;
		uint64_t rint_27:1;
		uint64_t rint_26:1;
		uint64_t rint_25:1;
		uint64_t rint_24:1;
		uint64_t asx1:1;
		uint64_t asx0:1;
		uint64_t rint_21:1;
		uint64_t pip:1;
		uint64_t spx1:1;
		uint64_t spx0:1;
		uint64_t lmc:1;
		uint64_t l2c:1;
		uint64_t rint_15:1;
		uint64_t rint_14:1;
		uint64_t rint_13:1;
		uint64_t pow:1;
		uint64_t tim:1;
		uint64_t pko:1;
		uint64_t ipd:1;
		uint64_t rint_8:1;
		uint64_t zip:1;
		uint64_t dfa:1;
		uint64_t fpa:1;
		uint64_t key:1;
		uint64_t npi:1;
		uint64_t gmx1:1;
		uint64_t gmx0:1;
		uint64_t mio:1;
#else
		uint64_t mio:1;
		uint64_t gmx0:1;
		uint64_t gmx1:1;
		uint64_t npi:1;
		uint64_t key:1;
		uint64_t fpa:1;
		uint64_t dfa:1;
		uint64_t zip:1;
		uint64_t rint_8:1;
		uint64_t ipd:1;
		uint64_t pko:1;
		uint64_t tim:1;
		uint64_t pow:1;
		uint64_t rint_13:1;
		uint64_t rint_14:1;
		uint64_t rint_15:1;
		uint64_t l2c:1;
		uint64_t lmc:1;
		uint64_t spx0:1;
		uint64_t spx1:1;
		uint64_t pip:1;
		uint64_t rint_21:1;
		uint64_t asx0:1;
		uint64_t asx1:1;
		uint64_t rint_24:1;
		uint64_t rint_25:1;
		uint64_t rint_26:1;
		uint64_t rint_27:1;
		uint64_t rint_28:1;
		uint64_t rint_29:1;
		uint64_t iob:1;
		uint64_t rint_31:1;
		uint64_t reserved_32_63:32;
#endif
	} cn38xx;
	struct cvmx_npi_rsl_int_blocks_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_31_63:33;
		uint64_t iob:1;
		uint64_t lmc1:1;
		uint64_t agl:1;
		uint64_t reserved_24_27:4;
		uint64_t asx1:1;
		uint64_t asx0:1;
		uint64_t reserved_21_21:1;
		uint64_t pip:1;
		uint64_t spx1:1;
		uint64_t spx0:1;
		uint64_t lmc:1;
		uint64_t l2c:1;
		uint64_t reserved_15_15:1;
		uint64_t rad:1;
		uint64_t usb:1;
		uint64_t pow:1;
		uint64_t tim:1;
		uint64_t pko:1;
		uint64_t ipd:1;
		uint64_t reserved_8_8:1;
		uint64_t zip:1;
		uint64_t dfa:1;
		uint64_t fpa:1;
		uint64_t key:1;
		uint64_t npi:1;
		uint64_t gmx1:1;
		uint64_t gmx0:1;
		uint64_t mio:1;
#else
		uint64_t mio:1;
		uint64_t gmx0:1;
		uint64_t gmx1:1;
		uint64_t npi:1;
		uint64_t key:1;
		uint64_t fpa:1;
		uint64_t dfa:1;
		uint64_t zip:1;
		uint64_t reserved_8_8:1;
		uint64_t ipd:1;
		uint64_t pko:1;
		uint64_t tim:1;
		uint64_t pow:1;
		uint64_t usb:1;
		uint64_t rad:1;
		uint64_t reserved_15_15:1;
		uint64_t l2c:1;
		uint64_t lmc:1;
		uint64_t spx0:1;
		uint64_t spx1:1;
		uint64_t pip:1;
		uint64_t reserved_21_21:1;
		uint64_t asx0:1;
		uint64_t asx1:1;
		uint64_t reserved_24_27:4;
		uint64_t agl:1;
		uint64_t lmc1:1;
		uint64_t iob:1;
		uint64_t reserved_31_63:33;
#endif
	} cn50xx;
};

union cvmx_npi_size_inputx {
	uint64_t u64;
	struct cvmx_npi_size_inputx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t size:32;
#else
		uint64_t size:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

union cvmx_npi_win_read_to {
	uint64_t u64;
	struct cvmx_npi_win_read_to_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t time:32;
#else
		uint64_t time:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
};

#endif