_ovr_bp_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_11_63:53;
		uint64_t en:3;
		uint64_t reserved_7_7:1;
		uint64_t bp:3;
		uint64_t reserved_3_3:1;
		uint64_t ign_full:3;
#else
		uint64_t ign_full:3;
		uint64_t reserved_3_3:1;
		uint64_t bp:3;
		uint64_t reserved_7_7:1;
		uint64_t en:3;
		uint64_t reserved_11_63:53;
#endif
	} cn30xx;
	struct cvmx_gmxx_tx_ovr_bp_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_12_63:52;
		uint64_t en:4;
		uint64_t bp:4;
		uint64_t ign_full:4;
#else
		uint64_t ign_full:4;
		uint64_t bp:4;
		uint64_t en:4;
		uint64_t reserved_12_63:52;
#endif
	} cn38xx;
	struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_48_63:16;
		uint64_t tx_prt_bp:16;
		uint64_t reserved_10_31:22;
		uint64_t en:2;
		uint64_t reserved_6_7:2;
		uint64_t bp:2;
		uint64_t reserved_2_3:2;
		uint64_t ign_full:2;
#else
		uint64_t ign_full:2;
		uint64_t reserved_2_3:2;
		uint64_t bp:2;
		uint64_t reserved_6_7:2;
		uint64_t en:2;
		uint64_t reserved_10_31:22;
		uint64_t tx_prt_bp:16;
		uint64_t reserved_48_63:16;
#endif
	} cnf71xx;
};

union cvmx_gmxx_tx_prts {
	uint64_t u64;
	struct cvmx_gmxx_tx_prts_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_5_63:59;
		uint64_t prts:5;
#else
		uint64_t prts:5;
		uint64_t reserved_5_63:59;
#endif
	} s;
};

union cvmx_gmxx_tx_spi_ctl {
	uint64_t u64;
	struct cvmx_gmxx_tx_spi_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t tpa_clr:1;
		uint64_t cont_pkt:1;
#else
		uint64_t cont_pkt:1;
		uint64_t tpa_clr:1;
		uint64_t reserved_2_63:62;
#endif
	} s;
};

union cvmx_gmxx_tx_spi_max {
	uint64_t u64;
	struct cvmx_gmxx_tx_spi_max_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_23_63:41;
		uint64_t slice:7;
		uint64_t max2:8;
		uint64_t max1:8;
#else
		uint64_t max1:8;
		uint64_t max2:8;
		uint64_t slice:7;
		uint64_t reserved_23_63:41;
#endif
	} s;
	struct cvmx_gmxx_tx_spi_max_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t max2:8;
		uint64_t max1:8;
#else
		uint64_t max1:8;
		uint64_t max2:8;
		uint64_t reserved_16_63:48;
#endif
	} cn38xx;
};

union cvmx_gmxx_tx_spi_thresh {
	uint64_t u64;
	struct cvmx_gmxx_tx_spi_thresh_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_6_63:58;
		uint64_t thresh:6;
#else
		uint64_t thresh:6;
		uint64_t reserved_6_63:58;
#endif
	} s;
};

union cvmx_gmxx_tx_xaui_ctl {
	uint64_t u64;
	struct cvmx_gmxx_tx_xaui_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_11_63:53;
		uint64_t hg_pause_hgi:2;
		uint64_t hg_en:1;
		uint64_t reserved_7_7:1;
		uint64_t ls_byp:1;
		uint64_t ls:2;
		uint64_t reserved_2_3:2;
		uint64_t uni_en:1;
		uint64_t dic_en:1;
#else
		uint64_t dic_en:1;
		uint64_t uni_en:1;
		uint64_t reserved_2_3:2;
		uint64_t ls:2;
		uint64_t ls_byp:1;
		uint64_t reserved_7_7:1;
		uint64_t hg_en:1;
		uint64_t hg_pause_hgi:2;
		uint64_t reserved_11_63:53;
#endif
	} s;
};

#endif