#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_3	723
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_4	724
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_5	725
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_6	726
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_7	727
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_8	728
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_9	729
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_10	730
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_11	731
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_12	732
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_13	733
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_14	734
#define CMDQ_EVENT_VDO1_BUF_UNDERRUN_ENG_15	735
#define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE	736
#define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE	737
#define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE	738
#define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE	739
#define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE	740
#define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE	741
#define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE	742
#define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE	743

#define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM	745
#define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM	746
#define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM	747
#define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM	748
#define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM	749
#define CMDQ_EVENT_VDO1_VPP_MERGE0	750
#define CMDQ_EVENT_VDO1_VPP_MERGE1	751
#define CMDQ_EVENT_VDO1_VPP_MERGE2	752
#define CMDQ_EVENT_VDO1_VPP_MERGE3	753
#define CMDQ_EVENT_VDO1_VPP_MERGE4	754
#define CMDQ_EVENT_VDO1_HDMITX	755
#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM	756
#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM	757
#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM	758
#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM	759
#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM	760
#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM	761
#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM	762

#define CMDQ_EVENT_CAM_A_PASS1_DONE	769
#define CMDQ_EVENT_CAM_B_PASS1_DONE	770
#define CMDQ_EVENT_GCAMSV_A_PASS1_DONE	771
#define CMDQ_EVENT_GCAMSV_B_PASS1_DONE	772
#define CMDQ_EVENT_MRAW_0_PASS1_DONE	773
#define CMDQ_EVENT_MRAW_1_PASS1_DONE	774
#define CMDQ_EVENT_MRAW_2_PASS1_DONE	775
#define CMDQ_EVENT_MRAW_3_PASS1_DONE	776
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL_X	777
#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL_X	778
#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL	779
#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL	780
#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL	781
#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL	782
#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL	783
#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL	784
#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL	785
#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL	786
#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL_X	787
#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL_X	788
#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL_X	789
#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL_X	790
#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT_X0	791
#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT_X0	792
#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT	793
#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT	794
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT	795
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT	796
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT	797
#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT	798
#define CMDQ_EVENT_U_CAMSYS_PDA_IRQO_EVENT_DONE_D1	799
#define CMDQ_EVENT_SUBB_TG_INT4	800
#define CMDQ_EVENT_SUBB_TG_INT3	801
#define CMDQ_EVENT_SUBB_TG_INT2	802
#define CMDQ_EVENT_SUBB_TG_INT1	803
#define CMDQ_EVENT_SUBA_TG_INT4	804
#define CMDQ_EVENT_SUBA_TG_INT3	805
#define CMDQ_EVENT_SUBA_TG_INT2	806
#define CMDQ_EVENT_SUBA_TG_INT1	807
#define CMDQ_EVENT_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	808
#define CMDQ_EVENT_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	809
#define CMDQ_EVENT_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	810
#define CMDQ_EVENT_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	811
#define CMDQ_EVENT_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	812
#define CMDQ_EVENT_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	813
#define CMDQ_EVENT_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	814
#define CMDQ_EVENT_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	815
#define CMDQ_EVENT_GCE1_SOF_0	816
#define CMDQ_EVENT_GCE1_SOF_1	817
#define CMDQ_EVENT_GCE1_SOF_2	818
#define CMDQ_EVENT_GCE1_SOF_3	819
#define CMDQ_EVENT_GCE1_SOF_4	820
#define CMDQ_EVENT_GCE1_SOF_5	821
#define CMDQ_EVENT_GCE1_SOF_6	822
#define CMDQ_EVENT_GCE1_SOF_7	823
#define CMDQ_EVENT_GCE1_SOF_8	824
#define CMDQ_EVENT_GCE1_SOF_9	825
#define CMDQ_EVENT_GCE1_SOF_10	826
#define CMDQ_EVENT_GCE1_SOF_11	827
#define CMDQ_EVENT_GCE1_SOF_12	828
#define CMDQ_EVENT_GCE1_SOF_13	829
#define CMDQ_EVENT_GCE1_SOF_14	830
#define CMDQ_EVENT_GCE1_SOF_15	831

#define CMDQ_EVENT_VDEC_LAT_LINE_COUNT_THRESHOLD_INTERRUPT	832
#define CMDQ_EVENT_VDEC_LAT_VDEC_INT	833
#define CMDQ_EVENT_VDEC_LAT_VDEC_PAUSE	834
#define CMDQ_EVENT_VDEC_LAT_VDEC_DEC_ERROR	835
#define CMDQ_EVENT_VDEC_LAT_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	836
#define CMDQ_EVENT_VDEC_LAT_VDEC_FRAME_DONE	837
#define CMDQ_EVENT_VDEC_LAT_INI_FETCH_RDY	838
#define CMDQ_EVENT_VDEC_LAT_PROCESS_FLAG	839
#define CMDQ_EVENT_VDEC_LAT_SEARCH_START_CODE_DONE	840
#define CMDQ_EVENT_VDEC_LAT_REF_REORDER_DONE	841
#define CMDQ_EVENT_VDEC_LAT_WP_TBLE_DONE	842
#define CMDQ_EVENT_VDEC_LAT_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	843
#define CMDQ_EVENT_VDEC_LAT_GCE_CNT_OP_THRESHOLD	847

#define CMDQ_EVENT_VDEC_LAT1_LINE_COUNT_THRESHOLD_INTERRUPT	848
#define CMDQ_EVENT_VDEC_LAT1_VDEC_INT	849
#define CMDQ_EVENT_VDEC_LAT1_VDEC_PAUSE	850
#define CMDQ_EVENT_VDEC_LAT1_VDEC_DEC_ERROR	851
#define CMDQ_EVENT_VDEC_LAT1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	852
#define CMDQ_EVENT_VDEC_LAT1_VDEC_FRAME_DONE	853
#define CMDQ_EVENT_VDEC_LAT1_INI_FETCH_RDY	854
#define CMDQ_EVENT_VDEC_LAT1_PROCESS_FLAG	855
#define CMDQ_EVENT_VDEC_LAT1_SEARCH_START_CODE_DONE	856
#define CMDQ_EVENT_VDEC_LAT1_REF_REORDER_DONE	857
#define CMDQ_EVENT_VDEC_LAT1_WP_TBLE_DONE	858
#define CMDQ_EVENT_VDEC_LAT1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	859
#define CMDQ_EVENT_VDEC_LAT1_GCE_CNT_OP_THRESHOLD	863

#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_0	864
#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_1	865

#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_8	872
#define CMDQ_EVENT_VDEC_SOC_GLOBAL_CON_250_9	873

#define CMDQ_EVENT_VDEC_CORE_LINE_COUNT_THRESHOLD_INTERRUPT	896
#define CMDQ_EVENT_VDEC_CORE_VDEC_INT	897
#define CMDQ_EVENT_VDEC_CORE_VDEC_PAUSE	898
#define CMDQ_EVENT_VDEC_CORE_VDEC_DEC_ERROR	899
#define CMDQ_EVENT_VDEC_CORE_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	900
#define CMDQ_EVENT_VDEC_CORE_VDEC_FRAME_DONE	901
#define CMDQ_EVENT_VDEC_CORE_INI_FETCH_RDY	902
#define CMDQ_EVENT_VDEC_CORE_PROCESS_FLAG	903
#define CMDQ_EVENT_VDEC_CORE_SEARCH_START_CODE_DONE	904
#define CMDQ_EVENT_VDEC_CORE_REF_REORDER_DONE	905
#define CMDQ_EVENT_VDEC_CORE_WP_TBLE_DONE	906
#define CMDQ_EVENT_VDEC_CORE_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	907
#define CMDQ_EVENT_VDEC_CORE_GCE_CNT_OP_THRESHOLD	911

#define CMDQ_EVENT_VDEC_CORE1_LINE_COUNT_THRESHOLD_INTERRUPT	912
#define CMDQ_EVENT_VDEC_CORE1_VDEC_INT	913
#define CMDQ_EVENT_VDEC_CORE1_VDEC_PAUSE	914
#define CMDQ_EVENT_VDEC_CORE1_VDEC_DEC_ERROR	915
#define CMDQ_EVENT_VDEC_CORE1_MC_BUSY_OVERFLOW_MDEC_TIMEOUT	916
#define CMDQ_EVENT_VDEC_CORE1_VDEC_FRAME_DONE	917
#define CMDQ_EVENT_VDEC_CORE1_INI_FETCH_RDY	918
#define CMDQ_EVENT_VDEC_CORE1_PROCESS_FLAG	919
#define CMDQ_EVENT_VDEC_CORE1_SEARCH_START_CODE_DONE	920
#define CMDQ_EVENT_VDEC_CORE1_REF_REORDER_DONE	921
#define CMDQ_EVENT_VDEC_CORE1_WP_TBLE_DONE	922
#define CMDQ_EVENT_VDEC_CORE1_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	923
#define CMDQ_EVENT_VDEC_CORE1_CNT_OP_THRESHOLD	927

#define CMDQ_EVENT_VENC_TOP_FRAME_DONE	929
#define CMDQ_EVENT_VENC_TOP_PAUSE_DONE	930
#define CMDQ_EVENT_VENC_TOP_JPGENC_DONE	931
#define CMDQ_EVENT_VENC_TOP_MB_DONE	932
#define CMDQ_EVENT_VENC_TOP_128BYTE_DONE	933
#define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE	934
#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_DONE	935
#define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE	936
#define CMDQ_EVENT_VENC_TOP_JPGDEC_C1_INSUFF_DONE	937
#define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE	938
#define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE	939
#define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE	940
#define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE	941
#define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE	942

#define CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE	945
#define CMDQ_EVENT_VENC_CORE1_TOP_PAUSE_DONE	946
#define CMDQ_EVENT_VENC_CORE1_TOP_JPGENC_DONE	947
#define CMDQ_EVENT_VENC_CORE1_TOP_MB_DONE	948
#define CMDQ_EVENT_VENC_CORE1_TOP_128BYTE_DONE	949
#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_DONE	950
#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_DONE	951
#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_INSUFF_DONE	952
#define CMDQ_EVENT_VENC_CORE1_TOP_JPGDEC_C1_INSUFF_DONE	953
#define CMDQ_EVENT_VENC_CORE1_TOP_WP_2ND_STAGE_DONE	954
#define CMDQ_EVENT_VENC_CORE1_TOP_WP_3RD_STAGE_DONE	955
#define CMDQ_EVENT_VENC_CORE1_TOP_PPS_HEADER_DONE	956
#define CMDQ_EVENT_VENC_CORE1_TOP_SPS_HEADER_DONE	957
#define CMDQ_EVENT_VENC_CORE1_TOP_VPS_HEADER_DONE	958

#define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE	962
#define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT	963

#define CMDQ_EVENT_WPE_VPP1_WPE_GCE_FRAME_DONE	969
#define CMDQ_EVENT_WPE_VPP1_WPE_DONE_SYNC_OUT	970

#define CMDQ_EVENT_DP_TX_VBLANK_FALLING	994
#define CMDQ_EVENT_DP_TX_VSC_FINISH	995

#define CMDQ_EVENT_OUTPIN_0	1018
#define CMDQ_EVENT_OUTPIN_1	1019

/* end of hw event */
#define CMDQ_MAX_HW_EVENT				1019

#endif